• Target DDR3 controllers development for Frame buffer (one frame delay) • Features Frame Buffer input: 1920 x 1080@60 fps, YUV 4:2:2 output: 1920 x 1080@60fps, YUV 4:2:2 • HW Platform DDR3 controller… (Budget: $1500 – $3000 USD, Jobs: Electrical Engineering, Electronics, FPGA, Microcontroller, Verilog / VHDL)
