CPLD Altera in Max Plus II by mariuszniewczas

I have problem with programmable system from family Altera Max 700B (EPM7256BQC208-7). When I compiler program timer in VHDL language I have error and I don’t know what I must do. Please help me. I add… (Budget: $30-$40 USD, Jobs: Electrical Engineering, Electronics, Microcontroller, Verilog / VHDL)