FPGA/VHDL Project and Report

I need a ZIP file including: – a report in PDF following an IEEE paper format – a folder with VHDL codes (at least 2 VHDL files are expected) – a TCL script and a file wave.do – Use QuestaSim/ModelSim… (Budget: £20 – £250 GBP, Jobs: Digital Design, Electrical Engineering, Electronics, FPGA, Verilog / VHDL)