implemetation AES for real time image using verilog on FPGA by viswa409

The goal of this project is to implement the Rijndael (AES) encryption system using Verilog. To do this, several separate sections of the algorithm will be coded to work together towards the end goal of performing the correct encryption routines… (Budget: ?1500-?12500 INR, Jobs: Marketing, Verilog / VHDL)